The FMC-GB-QSFP28 module is powered by Broadcom 100Gbps Gearbox PHY (BCM82790)that multiplexes and de-multiplexes four 25 Gbps channels to/from ten 10Gbps channels supporting Ethernet and Optical Transport Networking (OTN). The module supports one full-duplex 100Gbe port and complies with 100GBASE-CR4/SR4/LR4 for QSFP28 line-card applications. 100GbE Ethernet support includes CL91 RS FEC as well as CL92 transmit training, and CL73 auto-negotiation.
Test and debug features included in the Gearbox are PRBS pattern generation and checking, eye monitoring on all data receive interfaces, programmable loopbacks, as well as JTAG. Every port on the chip is equipped with an eye monitor. All features are accessed through an IEEE standard MDIO control interface.
The other Gearbox BCM82790 features include:
►Full-duplex, ten lane-to-four lane Gearbox via IEEE 802.3ba Clause 83 PMA
►Full-duplex, ten lanes to four lanes Gearbox via ITU OTL4.4
►Three-dimensional eye mapper on each high-speed receiver (14 total)
►Transmit preemphasis and adaptive receive equalization on all data I/Os
►Fully adaptive 25 Gbps receivers with 30 dB EQ
►Fully adaptive 10 Gbps receivers with 27 dB EQ
►Programmable drivers individually configurable voltage swing and preemphasis
►Supports IEEE 802.3bj Clause 91 Forward Error Correction (FEC) and bypassable.
►Supports OTU4/OTU2/OTU2e rates
►Line-side and system-side loopbacks
►Includes 1EEE802.3ap CL73 auto-negotiation
►IEEE802.3bj CL92 100G Ethernet (CR4) Tx Training
►IEEE802.3bj CL93 100G Ethernet (KR4) Tx Training
►For Ethernet: 156.25/161.13/312.50/322.26/625.00/644.50 MHZ reference clocks are supported.
►Standard, two-wire serial interface (BSC) support for external modules.
►Low-speed module, I/O control signals for CFP2,CFP4,and QSFP28
►MDIO interface-compliant to IEEE 802.3ae Clause 45
►Advanced diagnostics includes nonintrusive eye mapping and BER with PRBS generators/checkers
►MDIO signalling at 1.2V or 3.3V
►Interrupt pin with an array of maskable interrupt events
►Three-dimensional internal eye mapper on each lineside and system-side receiver
►Fixed 16-bit pattern generators and checkers on both line and system sides
►I2C master interfaces for QSFP28 control
►GPIOs for QSFP28 control pins
Additional product information is avilable at http://hitechglobal.com/FMCModules/FMC_GB_QSFP28.htm