Hybrid Memory Cube (HMC) represents a fundamental change in memory construction and connectivity. Utilizing 3D interconnect technology, HMC integrates the best of logic and DRAM processes into a heterogeneous package. HMC is constructed with a small logic layer below vertical stacks of DRAM die connected by through-silicon via (TSV) bonds. An energy optimized DRAM array provides efficient access to memory bits via the logic layer.
HMC represents the key to extending network system performance to push through the challenges of new 100G and 400G infrastructure growth with the following advantages:
-Increased Bandwidth - A single HMC unit can provide more than 15X the bandwidth of a DDR3 module.
-Reduced Latency – Provides lower queue delays and higher bank availability with vastly more built-in responders.
-Efficient Power — Utilizes 70% less energy per bit than DDR3 DRAM technologies.
-Built-in Reliability, Availability, and Serviceability (RAS) -Supports functions such as array and DRAM/LOGIC I/O Interface repair
-Smaller Physical Footprint — The stacked architecture uses nearly 90% less physical space than today’s RDIMMs.
-Pluggable to Multiple Platforms — Logic layer flexibility allows HMC to be tailored to multiple platforms and applications.
HiTech Global's Hybrid Memory Cube (HMC) Module
Leveraging form the latest FPGA, memory and High-Speed connector technologies, the ZR-HMC daughter card provides easy and high-performance interface to the latest HiTech Global's FPGA development boards populated by Xilinx Kintex / Virtex UltraScale and Altera Arria10 / Stratix 10 FPGA devices. The high-speed interface is done through Samtec Z-RAY connector offering the lowest profile and highest performance micro-interposer offered by the industry. The innovative layered design of the Z-RAY enables 56+ Gbps speeds, up to 3,000 cycles and profile as low as 0.3mm.
The ZR-HMC module is populated with one 2GB Micron MT43A4G40200NFAS15 Hybrid Memory Cube device and two Z-RAY interfaces. Multiple HMC devices may be chained together to increase the total memory capacity available to a host. As shown by the below diagram, the "Host" Z-RAY connector mates with FPGA carrier boards using 16 serial transceivers. The "Pass-Through" link mates with another ZR-HMC module for increasing the memory density beyond 2GB.